High Resistivity Wafers

Normal silicon wafer substrate resistivity ranges for CMOS technologies have typically spanned from a low of about 5 mohm-cm on heavily doped epi substrates to a high of around 30 ohm-cm on polished wafers. Although heavily doped substrates have proven useful for protection against latch-up, digital CMOS device design and performance has not been strongly coupled directly to substrate resistivity. This is changing in the emerging area of CMOS integration of radio frequency transceiver devices operating in the GHz frequency range.

Wireless chip designs can benefit significantly from higher substrate resistivity levels. Improvements in the performance of passive components, such as inductors, and substrate electrical isolation between the integrated digital, RF (radio frequency), and analog components are possible with higher resistivity silicon substrates Substrate resistivities greater than 40 ohm-cm are required now and in some cases resistivities in excess of 1000 ohm-cm will be needed.